1. Technical Field of the Invention
The present invention relates to monitoring power supplies, and particularly to a circuit and method for detecting voltage supply levels provided to an integrated circuit chip.
2. Description of the Related Art
Advancements in the semiconductor industry have led to increased demands for circuit performance. In an effort to more tightly control operating conditions so as to meet the increased demands placed on integrated circuitry, some existing integrated circuitry monitor power supply levels, such as the voltage supply level from an unregulated power supply, so as to detect instances in which the power supply level falls below a predetermined level, such as a predetermined minimum voltage level.
One existing power supply monitor circuit is shown in FIG. 1. An unregulated voltage is generated from a voltage divider of an unregulated power supply. A comparator C compares the unregulated voltage to a predetermined voltage reference Vref. The comparator C asserts a power fail signal PFO in the event the unregulated voltage falls below the predetermined voltage reference Vref. The power fail signal PFO may be, for example, provided to a processor or other controller device. Upon the power fail signal PFO being asserted, the processor/controller device may take appropriate remedial action, such as switching to a battery backup supply.
An existing voltage reference circuit 1 for generating the predetermined voltage reference Vref is shown in FIG. 2. The existing voltage reference may be seen as a unity gain differential amplifier 2 that forms a voltage follower circuit with voltage divider circuit 3. The voltage follower circuit is a trim circuit that provides a trimmed offset voltage to the comparator C, predetermined voltage reference Vref, that is relatively precisely set.
In particular, the existing voltage reference circuit 1 includes a bandgap reference circuit 8 that generates reference signal PFIref. The unity gain differential amplifier 2 receives reference signal PFIref at a first input and generates an output signal n3 that is provided to the input of voltage divider circuit 3. Voltage divider circuit 3 includes a series connected string of resistors R. Connected in parallel with resistors R is one or more fuse elements 4. The fuse elements 4 are selectively blown so as to relatively precisely trim the voltage across the resistor string. The output Vref of voltage divider circuit 3, which is provided to the comparator C of FIG. 1, is taken from a voltage appearing along the string of series connected resistors R.
The existing voltage reference circuit 1 of FIG. 2 allows for trimming the output signal PFIref of the bandgap reference circuit 8 in either the positive or negative direction. Specifically, the existing voltage reference circuit 1 of FIG. 2 includes programmable circuitry 5 that generates control signals nt and nc, first multiplexing circuitry 6 and second multiplexing circuitry 7. First multiplexing circuitry 6 selects as feedback to a second input of unity gain differential amplifier 2 one of two voltage signals tapped from the series connected string of resistors R. The selection of the feedback signal is based upon the value of signals nt and nc. Similarly, second multiplexing circuitry 7 selects as the signal provided to comparator C one of the two voltage signals tapped from the string of resistors R. The selected signal is also based upon signals nt and nc. The control of first and second multiplexing circuits 6 and 7 by signals nt and nc is such that the bottom of the resistor string is provided as the feedback signal for differential amplifier 2 and the top of the resistor string is coupled to the reference signal Vref when a positive trim offset voltage is to be added to reference signal PFIref. Alternatively, the top of the resistor string is provided as the feedback signal for differential amplifier 2 and the bottom of the resistor string is coupled to the reference signal Vref when a negative trim offset voltage is to be added to reference signal PFIref.
One problem with existing power supply monitor circuits, such as the existing power supply monitor circuitry of FIGS. 1 and 2, is in monitoring a relatively slowly changing unregulated power supply. For instance, a slowly changing unregulated voltage at or near the predetermined reference voltage Vref may cause comparator C to oscillate. As can be seen, oscillation of comparator C may cause the corresponding processor/controller device to attempt repeated remedial measures and/or otherwise disrupt the operation of the system. Based upon the foregoing, there is a need for a power supply monitor circuit that precisely monitors a power supply without the potential to oscillate.
Embodiments of the present invention overcome shortcomings in existing power supply monitor circuits and satisfy a significant need for a substantially oscillation-free monitor circuit. Embodiments of the present invention utilize hysteresis so as to avoid oscillation due to a slowly changing unregulated supply voltage. In particular, hysteresis circuitry is incorporated into the above-described power supply monitor circuitry. The hysteresis circuitry varies the amount of the trim offset voltage applied to the output of the bandgap reference voltage signal PFIref based upon the state of the power fail signal PFO generated by a comparator.
In an embodiment of the present invention, the total resistance of the resistor string (and hence the amount of the trim offset voltage) is varied based upon power fail signal PFO. In other embodiments of the present invention, the reference signal Vref of the voltage follower circuit is tapped from any one of a plurality of locations along the resistor string based upon the state of the power fail signal PFO, thereby selectively adjusting the trim offset voltage.
The operation of the power supply monitor circuit includes selectively blowing fuses in the resistor string to achieve the desired voltage drop across the resistor string. Next, a determination is made as to whether a positive or negative trim offset voltage is to be applied to the output PFIref of the bandgap reference circuit. Thereafter, the reference signal Vref of the voltage follower is a trimmed offset voltage, with the amount of trim offset voltage being a first offset voltage when the unregulated supply voltage is greater than reference signal Vref and a second offset voltage when the unregulated supply voltage is less than the reference signal Vref.